1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device having a multi-layer interconnection structure and a manufacturing method thereof.
2. Description of the Background Art
FIGS. 40A to 40F are views illustrating a related art structure of a semiconductor device having a multi-layer interconnection structure and a manufacturing method thereof. Referring to FIG. 40A, reference numeral 0 designates a silicon substrate; 1 is a trench isolation region; 2 is a gate oxide film; and 3 is a gate silicon film deposited by low pressure CVD (Chemical Vapor Deposition). The gate silicon film 3 is made from polysilicon or amorphous silicon doped with an impurity such as phosphorus (P) or arsenic (As).
In FIG. 40A, reference numeral 4 is a silicon oxide film deposited by low pressure CVD, and 5 is a silicon nitride film deposited by low pressure CVD. The gate silicon film 3, the silicon oxide film 4 and the silicon nitride film 5 form a gate electrode. Reference numeral 6 designates a source/drain region formed at a specific location surrounded by the trench isolation region 1 and the gate electrode composed of the films 3 to 5. The source/drain regions 6 are elements for constituting a transistor in cooperation with the gate electrode composed of the films 3 to 5. If the transistor is of an N-type, the source/drain region 6 is formed by implanting an impurity such as phosphorus or arsenic in the silicon substrate 0; while, if the transistor is of a P-type, the source/drain region 6 is formed by implanting an impurity such as boron (B) in the silicon substrate 0.
Referring to FIG. 40B, a silicon oxide film 300 is deposited on the silicon substrate 0 to cover the gate electrode composed of the films 3 to 5 and the source/drain regions 6.
Referring to FIG. 40C, the silicon oxide film 300 is etched to form side walls 301 covering the side surfaces of the gate electrode composed of the films 3 to 5. After formation of the side walls 301, a doped silicon film 302 made from polysilicon or amorphous silicon doped with an impurity is deposited on the silicon substrate 0 to cover the gate electrode composed of the films 3 to 5 and the side walls 301. The doped silicon film 302 is made from silicon doped with phosphorus or arsenic if the transistor is of the N-type and is made from silicon doped with boron if the transistor is of the P-type.
Referring to FIG. 40D, the doped silicon film 302 is etched in such a manner that pad layers 303 connected to the source/drain regions are formed on both sides of the gate electrode composed of the films 3 to 5.
Referring to FIG. 40E, a silicon oxide film 304 is deposited on the pad layers 303 by CVD. A resist film 305 is formed on the silicon oxide film 304 and is patterned by photolithography. The silicon oxide film 304 is selectively etched using the patterned resist film 305 as a mask, to form contact holes 306 communicated to the pad layers 303.
Referring to FIG. 40F, the contact hole 306 is filled with polysilicon or amorphous silicon in such a manner that the filled-in silicon is connected to the pad layers 303, to form an interconnection layer 307. Polysilicon or amorphous silicon, which forms the interconnection layer 307, is doped with an impurity such as phosphorus or arsenic if the transistor is of the N-type and is doped with an impurity such as boron if the transistor is of the P-type.
In recent years, with the increased demands toward miniaturization of a semiconductor device, a dimensional allowable margin between the contact hole 306 and the gate electrode composed of the films 3 to 5 has come to be reduced. In such a situation, by use of the above-described pad layer 303, it is possible to ensure conduction between the interconnection layer 307 and the source/drain region 6 while preventing short-circuit between the interconnection layer 307 and the gate silicon film 3.
FIG. 41 is a cross-sectional view showing a second example of the related art semiconductor device. In FIG. 41, parts corresponding to those in FIG. 40 are designated by like reference numerals and explanation thereof is omitted.
Referring to FIG. 41, reference numeral 308 designates a high melting point metal film made from Ti, TiN or the like; 309 is a low resistance metal film made from W or the like; and 310 is a silicide film produced by reaction between a pad layer (doped polysilicon) 303 and the high melting point metal film 308.
An interconnection layer having a sufficiently low resistance can be formed by the high melting point metal film 308 and the low resistance metal film 309. The contact resistance at the contact boundary between the interconnection layer and the pad layer 303 can be sufficiently suppressed and also a desirable ohmic characteristic thereat can be ensured by the presence of the silicide layer 310 interposed between the interconnection layer and the pad layer 303. As a result, in the semiconductor device shown in FIG. 41, the resistance between a source/drain region 6 and the interconnection layer can be sufficiently suppressed.
FIGS. 42A to 42F and FIG. 43 are sectional views illustrating a manufacturing method in which a structure for connecting a source/drain region to an interconnection layer using a pad layer (hereinafter, referred to as xe2x80x9cpad structurexe2x80x9d) is applied to a DRAM (Dynamic Random Access Memory) as well as a structure of the DRAM fabricated by the manufacturing method. In these figures, parts corresponding to those in FIGS. 40A to 40E and FIG. 41 are designated by like reference numerals and explanation thereof is omitted.
In the case of applying the pad structure to a DRAM, as shown in FIG. 42A, after formation of a silicon nitride film 5, the wafer is subjected to oxidation treatment, to form an oxide layer on side surfaces of a gate silicon film 3. As a result, the upper and side portions of the gate silicon film 3 are covered with a silicon oxide film 4. Referring to FIG. 42B, a silicon nitride film 320 is deposited by CVD to cover the entire surface of a silicon substrate 0. Then, the silicon nitride film 320 is selectively etched using a patterned resist film 321 as a mask, to form a contact hole 322 opened to each source/drain region 6 between adjacent gate electrodes.
Referring to FIG. 42C, a pad layer 323 made from doped polysilicon or amorphous silicon is formed in each contact hole 322. In FIG. 42C, of the two pad layers 323, the left one is to be connected to an interconnection layer (bit line) of the DRAM, and the right one is to be connected to a storage node (capacitor) of the DRAM.
Referring to FIG. 42D, a silicon oxide film 324 is deposited on the entire surface of the silicon substrate 0 in such a manner as to cover the upper portions of the pad layers 323.
Referring to FIG. 42E, the silicon oxide film 324 is selectively etched using a patterned resist film 330 as a mask, to form a contact hole 331 opened to each pad layer 323 to be connected to an interconnection layer.
Referring to FIG. 42F, a high melting point metal film 333 made from Ti, TiN or the like is formed in such a manner as to cover the surface of the silicon oxide film 324, the side surface of each contact hole 331, and the surface of each pad layer 323. Then, a low resistance metal film 334 made from W or the like is formed on the high melting point metal film 333.
Referring to FIG. 43, the high melting point metal film 333 and the low resistance metal film 334 are selectively etched into a desired shape, to form an interconnection layer composed of the metal films 333 and 334. Then, the wafer is subjected to a specific heat treatment, to form a silicide film 335 near the boundary between the high melting point metal film 333 and the pad layer 323.
After that, a first electrode of a capacitor is formed in such a manner as to be connected to the pad layer 323 for a capacitor. Then, an insulating film and a second electrode are sequentially formed thereon. A memory cell structure of the DRAM is thus realized. In the case of applying the pad structure to the DRAM as described above, even if the dimensional margin is small, the interconnection layer and the capacitor can be certainly connected to the source/drain resin 6 without short-circuit with the gate silicon film 3; and the resistance between the source/drain region 6 and the interconnection layer can be sufficiently suppressed according to the above structure. In this way, by use of the pad structure, a DRAM having a high level of integration and good electric characteristics can be realized.
The above pad structure, however, has problems. For example, in the pad structure shown in FIG. 40F and FIG. 41, the pad layer 303 is provided with a large stepped portion. Similarly, in the pad structure shown in FIG. 43, the pad layer 323 is provided with a large stepped portion. In the case where the pad layer 303 or 323 has such a large stepped portion, it is very difficult to form the pattern by photolithography and etching and also to form the contact hole 306 or 322 opened to the pad layer 303 or 323 by etching. As a result, the above pad structure may cause an inconvenience such as short-circuit between the adjacent pad layers by an etching residue.
Further, in the case where the pad layer 303 or 323 has such a large stepped portion, the planarization of the interlayer insulating film, i.e., of the silicon oxide film 304 or 324 deposited on the pad layer 303 or 323 is made poor. Accordingly, the stepped portion of the pad layer 303 or 323 causes a problem that it is difficult to ensure a good processing accuracy of the interconnection layer formed on the interlayer insulating film.
In the pad structure shown in FIGS. 42A to 42F and FIG. 43, the pad layer 323 is provided between the two adjacent gate electrodes each being composed of the films 3 to 5 and a large recess is provided in the central portion of the pad layer 323, whereby the gap between the gate electrodes is made sufficiently smaller than the width of the contact hole 331 while ensuring enough contact surface. In such a pad structure, however, since the aspect ratio of the portion near the central portion of the pad layer 323 is high, the coverage of the conductive layer, that is, the high melting point metal film 333 or the first electrode of the capacitor formed on the pad layer 323 is made poor. Accordingly, the pad structure in which the pad layer 323 is provided between the two adjacent gate electrodes each being composed of the films 3 to 5 may cause a problem that the contact resistance near the pad layer 323 is increased and thereby the device characteristics are degraded.
Additionally, in the pad structure shown in FIG. 41 or 43 in which the high melting point metal film is formed on the pad layer 303 or 323, the coverage of the high melting point metal at the stepped portion of the pad layer 303 or 323 is apt to be degraded, with a result that the contact resistance at the portion near the pad layer 303 or 323 is increased. In particular, in the case where the coverage of the high melting point metal film 308 or 333 is poor, the pad layer 303 or 323 may be locally brought into contact with the low resistance metal film 309 or 334. The element W generally used for forming the low resistance metal film 309 or 334 has a property of absorbing an impurity from doped silicon. As a result, if the pad layer 303 or 323 is locally brought into contact with the low resistance metal film 309 or 334, there occurs an inconvenience such as a contact failure because of the absorption of the impurity from doped silicon by the element W.
In this way, according to the above-described pad structure, there arise various inconveniences resulting from the stepped portion of the pad layer 303 or 323. As a result, the above-described pad structure has a problem in degrading both the yield of the device and the reliability of the device.
The present invention has been conceived to solve the previously-mentioned problems, and a first object of the present invention is to provide a semiconductor device requiring a high level of integration, which is capable of ensuring a good yield and a high reliability.
A second object of the present invention is to provide a method of manufacturing a semiconductor device having a high level of integration, a good yield, and a high reliability.
The first object of the present invention is achieved by a semiconductor device as described below. The semiconductor device includes first and second circuit elements to be connected to each other. The two elements are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction. A first interlayer insulating film is formed on the first circuit element. A conductive pad is provided in the first interlayer insulating film in such a manner that one end surface thereof is connected to the first circuit element and the other end surface thereof is exposed to the surface of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film and the pad. A conductive plug is provided in the second interlayer insulating film in such a manner that one end surface thereof is in contact with the pad and the other end surface thereof is connected to the second circuit element. The surface of the first interlayer insulating film is smoothly continuous to the other end surface of the pad at the same level. The plug is smaller in size than the pad and is in contact with the central portion of the pad.
The second object of the present invention is achieved by a method of manufacturing a semiconductor device in which first and second circuit elements to be connected to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction. According to the method, a first interlayer insulating film is formed on the first circuit element. A conductive pad is provided in the first interlayer insulating film in such a manner that one end surface of the conductive pad is connected to the first circuit element. A second interlayer insulating film is formed on the first interlayer insulating film and the pad. A conductive plug is provided in the second interlayer insulating film in such a manner that one end surface of the conductive plug is in contact with the pad and the other end surface thereof is connected to the second circuit element. The step of forming the pad includes a step of forming the pad in such a manner that the other end surface of the pad is smoothly continuous to the surface of the first interlayer insulating film at the same level. Further, the plug is formed in such a manner as to be smaller in size than the pad and to be in contact with the central portion of the pad.
The first object of the present invention is also achieved be a semiconductor device described as below. The semiconductor device has a capacitor over bit line structure in which a capacitor is provided on a bit line. The semiconductor device further includes a transistor formed on a silicon substrate. The transistor includes two source/drain regions and a gate electrode held therebetween. A first interlayer insulating film is formed on the transistor. An interconnection side pad is provided in the first interlayer insulating film in such a manner that one end surface thereof is connected to one of the source/drain regions and the other end surface thereof is exposed to the surface of the first interlayer insulating film. A capacitor side pad is provided in the first interlayer insulating film in such a manner that one end surface thereof is connected to the other of the source/drain regions and the other end surface thereof is exposed to the surface of the first interlayer insulating film. A second interlayer insulating film formed on the first interlayer insulating film and the two pads. A bit line is formed on the second interlayer insulating film. An interconnection side plug is provided in the second interlayer insulating film in such a manner that one end surface thereof is in contact with the interconnection side pad and the other end surface thereof is connected to the bit line. A third interlayer insulating film is formed on the bit line and the second interlayer insulating film. A first electrode for a capacitor is formed on the third interlayer insulating film. A capacitor side plug is provided in the third interlayer insulating film in such a manner that one end surface thereof is in contact with the capacitor side pad and the other end surface thereof is connected to the first electrode. The surface of the first interlayer insulating film is smoothly continuous to the other end surfaces of the two pads at the same level. The interconnection side plug is smaller in size than the interconnection side pad, and is in contact with the central portion of the interconnection side pad. The capacitor side plug is smaller in size than the capacitor side pad, and is in contact with the central portion of the capacitor side pad. The interconnection side pad is made from doped silicon. The interconnection side plug includes a high melting point metal film being in contact with the interconnection side pad and a low resistance metal film formed on the high melting point metal side film. A silicide film is formed near the boundary between the interconnection side pad and the interconnection side plug. The silicide film is formed by reaction between the interconnection side pad and a first high melting point metal film suitable for preventing absorption of an impurity from the doped silicon. The high melting point metal film constituting part of the interconnection plug is a second high melting point metal film suitable for preventing reaction between the doped silicon and the low resistance metal film.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.